The name of the project:
"Super integrated low - voltage elements on the submicron merged semiconductor structures"

The content of the work:
The project concern to area of the silicon submicron technology and the future nanotechnology and consist in a development of an element base for the perspective microsystems.
The essence of the project consists in the new approach of an implementation of the integrated circuits elements, at which an active field of the semiconductor structure is formed in an intrinsic semiconductor of in non doped (low doped) semiconductor. It allows in the same active area of the device to operate by both types of the carriers, electrons and holes, that is to merge in one structure two various devices (n - channel and p - channel MOS transistors or bipolar npn and pnp transistors). As a result this merged semiconductor structure (MSS) is an integrated functional device, carrying out the certain circuit function - an amplification with an inverting. At the traditional approach in a composition of an element include at least two devices and interconnections, that is the several active fields with the various type of the conductivity. The transition to the MSS allow to implement the super integrated elements, ensuring on the order a higher level of integration, owing to the simplification of the construction and the increase of the functional complexity of the devices.
An application of the non doped active areas allow at most to decrease the supply voltage ( up to 0,5 V and lower), that cause the difficulties in the ordinary devices with the high doped fields. An use of the low doped areas till now was limited owing to the transistors breakdown (pinhole), but at the transition to the submicron dimensions this limitation is solved on the constructive base.
The transition to the MSS offer the possibility of an utmost scaling, that is the decrease of the sizes of elements down to sizes, at which determining become the quantum - dimensional effects.
It opens an opportunity of creation the lithography invariant elements, operating in a wide interval of the topological dimensions.
MSS are especially effective in a three dimensional implement. Thus their sizes decrease up to one minimal topological square, and the sizes of elements in view of isolation between them make no more ten minimal squares. Thus at the 0,1 μm technology the elements density exceed 108 gates/cm².
MSS give an essential prize and at a planar design, is especial at use of a isolated substrate.
In MSS it is possible in general to refuse from doping of semiconductors (or, at least, formation of local doped areas) and as materials of electrodes to use the metals and the metals silicides.
The forecasting advantages of MSS in comparison with the typical CMOS transistors are shown in a mentioned below table:

Technology	aaaa	aaaa	aaaa	Reference
Minimal feature size, μm	0.25	0.15	0.10	aaaa
Density of the typical MOS transistors/cm2	8M	16M	40M	SIA Roadmap
Density of MSS, gates/cm2	100M	200M	400M	Ours estimation
Minimal supply voltage, V	aaaa	aaaa	aaaa	aaaa
Typical CMOS circuits	1.8-2.5	1.2-2.5	0.9-1.2	aaaa
Supposed MSS circuits	0.7-0.5	0.7-0.5	0.6-0.4	aaaa

The realization the super integrated low voltage elements on the base MSS with the sizes in ten hundred parts of micron require the implement of the complex of the physical and technological researches and the constructive and circuit engineering developments. At the beginning it is necessary to execute an analysis and a modeling of the device construction, the technological routes of the manufacture, to realize their tie to the technological possibilities of the manufacturers, to develop the circuit engineering and an architecture of the integrated circuits on their base.


The expected results:
The construction and the technological route of the manufacture of the low voltage super integrated elements with the parameters:

supply voltage	0.5 - 0.7 V,
speed	1.0 - 10 GHz
level of integration	more 100 millions gates/cm2

The possible areas of the results application:
The submicron integrated circuits
The integrated circuits with the nanometer dimensions.