V.V. Rakitin, E.I. Filippov
Analysis and Simulation
We present the results of simulation of new device architecture - so-called
double-gate MOS transistors. The basic concept of a dual gate MOS transistor
is quite simple - p common channel is used in the transfer of carriers
of both signs. The new device may be an important step toward nanometer-scale
devices.
Many different dual -gate MOS transistor configurations exist, but
what they have in common is that the two transistor gates modulate the
channel's electronic properties. We have carried out the simulation of
vertical, planar and optical dual gate transistors.
Fig.1 Vertical dual-gate transistor.
Fig.2 Planar dual-gate transistor.
Fig.3 Cross section of an optical double-gate transistor
The double-gate transistor approach applies conventional technological processes to create the devices below 0.1 micron.
Properties of double-gate MOS transistors:
1.Double-gate transistor occupies the least possible area (one topological square);
2.Level of integration 108 -1010 logical elements per cm2;
3.Operate at low supply voltage 0.4-0.8 V.Double-gate MOS transistors can be fabricated using conventional technological processes.
Fig. 4 Current-voltage curves of a double-gate transistor.
It follows from the current - voltage curves and the transfer characteristic of an dual gate structure :
Studies of the new structure show that it can achieve acceptable electronic results. The dual gate device is more immune to short channel effect, that the single-gate structure. We believe that the dual gate structure will prove scalable to ultimate CMOS limit of 20-nm to 30-nm gate. Also, if the two gates can be accessed independently, the structure offers potential advantages in novel circuit architectures.
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